Power consumption is becoming an increasing concern in the design of integrated circuits (ICs), particularly for very large scale integration (VLSI) chip design. Increases in power consumption are outpacing the advantages of advances in scaling in silicon technologies, and the benefits of reducing power supply voltages. Power management has been recognized as an important consideration associated with the design and operation of VLSI (Very Large Scale Integration) chips to mitigate power consumption associated with VLSI chips. Consequently, approaches exist to adjust the supply voltage in response to changes in current drawn by the VLSI device.
For a variety of applications including the calibration of a power management system, it is desirable to generate a precise current with amperage in the same order of magnitude as that consumed by the VLSI device itself. Fabrication of precise current sources on VLSI devices is very difficult due to process variations associated with the fabrications of current sources, including those employing CMOS and Bipolar-CMOS technologies. In general, process variations can include lot-to-lot variations, wafer-to-wafer variations, die-to-die variations and within-die variations.